The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a boot-strap circuit acting as an output circuit.
FIG. 1 is a circuit diagram illustrative of a conventional semiconductor device having an output circuit which comprises a boot-strap circuit which will be described as follows. The semiconductor device has a first input terminal 1 and a second input terminal 2 as well as an output terminal 10. A series connection of a second n-MOS field effect transistor 8 and a third n-MOS field effect transistor 9 is provided between a high voltage line Vcc and a ground line GND, wherein the second n-MOS field effect transistor 8 is connected to the high voltage line Vcc, whilst the third n-MOS field effect transistor 9 is connected to the ground line GND. A first n-type MOS transistor 5 is connected in series between the first input terminal 1 and a gate electrode of the second n-MOS field effect transistor 8. The first n-type MOS transistor 5 is connected in series through a boot-strap node N3 to the gate electrode of the second n-MOS field effect transistor 8. The output terminal 10 is connected to an intermediate point between the second n-MOS field effect transistor 8 and the third n-MOS field effect transistor 9. A parasitic capacitance 7 is formed which is connected in series between the boot-strap node N3 and the intermediate point between the second n-MOS field effect transistor 8 and the third n-MOS field effect transistor 9. An odd staged delay circuit 3 is provided which has an input side which is connected to the first input terminal 1 as well as has an output side which is connected through a node N1 to a gate electrode of the first n-type MOS transistor 5. An invertor 4 is provided which has an input side which is connected through the node N1 to the output side of the odd staged delay circuit 3 as well as has an output side which is connected to a node N2. A capacitor 6 as a MOS capacitor is provided between the node N2 and the boot-strap node N3. The second input terminal 2 is directly connected to a gate of the third n-MOS field effect transistor 9.
FIG. 2 is a diagram illustrative of waveforms of a first input signal .phi..sub.T and a second input signal .phi..sub.N as well as signals at the nodes N1 and N2 and the boot-strap node N3 in addition an output signal OUT. The first input signal .phi..sub.T is applied to the first input terminal 1, whilst the second input signal .phi..sub.N is applied to the second input terminal 2. The nodes N1 and N2 have potentials which vary as illustrated in FIG. 2. The boot-strap node N3 has a potential which varies as illustrated in FIG. 2. Further, the output signal OUT appears at the output terminal 10. With reference to FIG. 2, the operations of the semiconductor device of FIG. 1 will be described.
In an initial time period, the first input signal .phi..sub.T remains in the GND level or the low level whilst the second input signal .phi..sub.N remains in the Vcc level or the high level. The first input signal .phi..sub.T having the GND level or the low level is inputted into the first input terminal 1 and then transmitted through the odd staged delay circuit 3 to the node N1, where the node N1 has the Vcc level or the high level. The signal is further transmitted through the invertor 4 to the node N2 where the node N2 has the GND level or the low level. Since the gate electrode of the first n-type MOS transistor 5 is connected to the node N1, the signal of the Vcc level or the high level is applied to the gate electrode of the first n-type MOS transistor 5 whereby the first n-type MOS transistor 5 remains ON. As a result, the boot-strap node N3 is electrically conductive to the first input terminal 1 so that the boot-strap node N3 receives the first input signal .phi..sub.T, for which reason the boot-strap node N3 has the GND level or the low level. Since the gate electrode of the second n-MOS field effect transistor 8 is connected to the boot-strap node N3, then the gate electrode of the second n-MOS field effect transistor 8 receives the GND level or low level signal supplied from the first input terminal 1 whereby the second n-MOS field effect transistor 8 remains OFF. This means that the intermediate point between the second n-MOS field effect transistor 8 and the third n-MOS field effect transistor 9 is isolated from the high voltage line Vcc. On the other hand, the second input signal .phi..sub.N being applied to the second input terminal 2 is the Vcc level or the high level. Since the gate electrode of the third n-MOS field effect transistor 9 is directly connected to the second input terminal 2, the gate electrode of the third n-MOS field effect transistor 9 receives the Vcc level or high level signal whereby the third n-MOS field effect transistor 9 remains ON. As a result, the intermediate point between the second n-MOS field effect transistor 8 and the third n-MOS field effect transistor 9 remains electrically conductive to the ground line GND whereby the intermediate point between the second n-MOS field effect transistor 8 and the third n-MOS field effect transistor 9 has the same potential as the ground level GND or the low level. Therefore, the output signal OUT is the GND level or the low level.
Subsequently, the first input signal .phi..sub.T is changed to the Vcc level or the high level while the second input signal .phi..sub.N is changed. The first input signal .phi..sub.T having the Vcc level or the high level is inputted into the odd staged delay circuit 3 so that the change to the GND level or the low level of the output from the odd staged delay circuit 3 is delayed by a predetermined time period from the change to the Vcc level or the high level of the first input signal .phi..sub.T. The predetermined time period is the factor depending upon the odd staged delay circuit 3. This means that, during the predetermined time period after the first input signal .phi..sub.T has been changed to the Vcc level or the high level, the node N1 remains in the Vcc level or the high level whereby the Vcc level or the high level is applied to the gate electrode of the first n-type MOS transistor 5. Namely, during the predetermined time period after the first input signal .phi..sub.T has been changed to the Vcc level or the high level, the first n-type MOS transistor 5 remains ON whereby the boot-strap node N3 remains conductive to the first input terminal 1 which has the Vcc level or the high level. Assuming that the first n-type MOS transistor 5 has a threshold voltage Vth in an ON state, the boot-strap node N3 is increased up to a voltage level (Vcc-Vth) and then remains at that voltage during the predetermined time period after the first input signal .phi..sub.T has been changed to the Vcc level or the high level. On the other hand, since the gate electrode of the third n-MOS field effect transistor 9 is directly connected to the second input terminal 2, then the gate electrode of the third n-MOS field effect transistor 9 receives the GND level or the low level whereby the third n-MOS field effect transistor 9 turns OFF, immediately after the second input signal .phi..sub.N has been changed to the GND level or the low level.
After the predetermined time period has passed, the output from the odd staged delay circuit 3 is changed to the GND level or the low level and remains that level subsequently. The gate of the first n-type MOS transistor 5 receives the GND level or low level gate signal whereby the first n-type MOS transistor 5 turns OFF. As a result, the boot-strap node N3 is isolated from the first input terminal 1. The GND level or low level signal from the odd staged delay circuit 3 is then inputted into the invertor 4. The output of the invertor 4 is changed to the Vcc level or high level signal. The Vcc level or high level signal is applied to the capacitor 6 whereby the potential of the boot-strap node N3 is booted up to a high voltage of Vcc+Vth or higher. The high voltage of Vcc+Vth or higher is applied to the gate electrode of the second n-MOS field effect transistor 8 whereby the second n-MOS field effect transistor 8 remains ON.
On the other hand, since the gate electrode of the third n-MOS field effect transistor 9 is directly connected to the second input terminal 2, then the gate electrode of the third n-MOS field effect transistor 9 receives the GND level or the low level whereby the third n-MOS field effect transistor 9 turns OFF, immediately after the second input signal .phi..sub.N has been changed to the GND level or the low level. The intermediate point between the second n-MOS field effect transistor 8 and the third n-MOS field effect transistor 9 is isolated from the ground line GND. During a time period when the boot-strap node N3 is booted from the GND level or the low level up to the high level of Vcc-Vth, the second n-MOS field effect transistor 8 turns ON when the potential of the boot-strap node N3 exceeds the threshold voltage Vth whereby the potential of the intermediate point between the second n-MOS field effect transistor 8 and the third n-MOS field effect transistor 9 is increased up to the high voltage level Vcc when the boot-strap node N3 is booted up to a high voltage of Vcc+Vth or higher. As a result, the output signal OUT becomes the high voltage level Vcc. Namely, the high level output is obtained.
It is now assumed that the potential of the boot-strap node N3 is further increased by .DELTA.V from the high voltage of Vcc+Vth or higher by any accidental cause. In this case, the output signal OUT is also booted by the parasitic capacitance 7 up to the high voltage of Vcc+.DELTA.V.
Normally, the output signal OUT is used as an input signal to be inputted into the other semiconductor device, for which reason it is required to prevent any excess increase in the voltage of the output signal OUT. Even the output signal OUT is increased up to the voltage of Vcc+Vth, there is no discharge pass unless the third n-MOS field effect transistor 9 turns ON to form a discharge pass which allows the charge through the third n-MOS field effect transistor 9 to the ground line GND.
Consequently, after the output signal OUT has been increased up to the high voltage, there is no discharge pass unless by changing the input signal, any discharge pass is formed. For that reason, if the potential of the boot-strap node N3 is further increased from the predetermined high voltage of Vcc+Vth or higher by any accidental cause, then the output signal OUT is also booted by the parasitic capacitance 7 up to the high voltage of Vcc+.DELTA.V. The output signal OUT is excessively booted up and inputted into the other semiconductor device as an input signal whereby the malfunction of the other semiconductor device will appear.
In the above circumstance, it had been required to develop a novel semiconductor circuitry which is capable of both controlling an output signal voltage level within a predetermined allowable voltage level range and of reducing the on voltage level of the output signal down into the predetermined allowable voltage level range even when the output signal voltage level is excessively booted up to a higher voltage level than the predetermined allowable voltage level range.